A. Field of the Invention
The present invention relates generally to the field of wireless communications. More particularly, the present invention relates to an adaptive-biased mixer for a wireless communication system.
B. Background
Recently, the demand for portable wireless communication systems has grown significantly, such as for wireless local area networks (LAN), home wireless control systems and wireless multimedia centers. With improved transistor scaling down technology and improved circuit techniques, more and more miniature chip systems, such as cellular phones, wireless network cards, personal radio messaging systems and control devices have emerged and been used by many people.
With many wireless devices working in the same frequency band, the interferences among these devices is becoming more and more severe. Current wireless systems require that the wireless devices be immune to off-channel interferences, whereby this requirement means that the wireless receiving devices need to become more linear. However, circuit linearity becomes worse as semiconductor technology scales down in size. This is primarily due to the fact that the supply voltage of a smaller feature size technology is generally smaller and the circuit voltage headroom becomes smaller as well, which hurts the circuit linearity. Although some technologies have the potential to support two different supply voltages, it is still hard to be used in a high frequency (e.g. radio frequency, or RF) application because high supply voltage devices are commonly used with lower speeds. Also, a double or triple supply voltage is not a viable option for wireless chip systems because of its complicated supply routing on a circuit board and the increased cost involved.
Thus, a high linear mixer that can work with a low supply voltage is a preferred choice to provide a highly linear wireless device. Since the noise figure of a down-conversion mixer affects the noise performance of the wireless receiver, low noise characteristics for the mixer are also preferred.
Another area that needs a highly linear mixer is a transmitter linearization loop. The portable characteristics of current wireless communication devices require power efficient receiving and transmitting. To meet this requirement, there has been performed research into the use of a low power transmitter, especially with respect to linearization techniques to enhance the linearity of power amplifiers and thereby avoid the in-band distortion and adjacent band interference. These linearization techniques are typically used in conjunction with the amplification of an amplitude-modulated signal, such as a QAM (Quadrature Amplitude Modulation) signal. This is because the power amplifier distorts the envelope of the fundamental frequency signal. With a linearization loop, the linear power amplifier can be achieved with a high power efficient non-linear power amplifier such as a class C or class E amplifier, which has much lower power consumption compared with the power hungry transmitter with a low efficiency linear power amplifier such as a class A amplifier. The additional power consumed by the linearization system needs to be considered in the calculation of the overall efficiency of the wireless communication system.
Several conventional linearization techniques are currently available. Table 1 characterizes these techniques by different properties. The first property distinguishes whether the technique is analog or digital. The second property distinguishes whether the technique is a compensation technique or a signal splitting technique.
TABLE 1Linearization TechniquesLinearizationAnalogDigitalCompensationCartesian Loop,Mapping Techniques,TechniquesPolar Loop,Complex Gain Predistortion,Envelope Feedback,Polar PredistortionPhase CorrectingFeedback,Feed ForwardSignal SplittingCALLUM,LINCTechniquesLINC,Envelope Eliminationand Restoration
Among these techniques, the Cartesian modulation feedback loop and Polar modulation feedback loop require a highly linear down-conversion mixer to boost the linearity of the transmitter. Since the Cartesian loop and the Polar loop are generally adopted in an integrated transmitter linearization implementation because of their simple architecture, and the transmitter linearity is determined by the linearity of the down-conversion mixer inside the loop, a highly linear mixer is desirable. For the same reasons as have been discussed in the receiver side, the mixer also needs to tolerate a low supply voltage.
A down-conversion mixer translates an incoming RF signal into a lower frequency by multiplying it with a local oscillation (LO) signal. With this frequency lowering technique, it becomes relatively easy to obtain the requisite gain in the receiver chain, accomplish the RF tuning by varying the local oscillator frequency, and distribute the gain over a number of different frequency bands to avoid the potential oscillation arising from parasitic feedback loops. Since the dynamic range requirements in modern high performance telecommunication systems are quite severe, approaching 100 dB in some instances, the higher onset of severe nonlinearities that accompany large input signals is better, which limits the ceiling of the system dynamic range. In a wireless receiver chain, the down-conversion mixer is an important component that restricts the increase of the dynamic range upper limit.
Since the invention of Armstrong's frequency translation technique about 70 years ago, many types of mixers have been utilized for RF communications systems, whereby the basic concept is to do frequency conversion through switching. With a trend starting in the 1990s to implement an RF system into a single CMOS chip, these circuit architectures are also used in CMOS technology. FIG. 1 shows a mixer circuit 100 that is a popular choice for conventional wireless receivers, whereby this mixer circuit corresponds to a Gilbert Multiplier architecture and belongs to the ‘active’ category of mixers. The RF signals are fed into the mixer circuit 100 through a differential pair RFP, RFN, whereby the mixer amplifies the RF signals and isolates the signal mixing with a first stage low noise amplifier (LNA). Four switching transistors driven by the LO signal LOP, LON (differential pair) with large swing perform the double-balanced frequency translation. The even-order nonlinearity can be cancelled through this balanced implementation. The mixer circuit 100 is biased with a DC current source that is provided with a BIAS signal input.
Some current implementations use half of the circuit to serve as a mixer to the single RF input, which corresponds to a single balanced counterpart to the double balanced structure shown in FIG. 1. To decrease the noise contribution from point A and B in the LO frequency as shown in FIG. 1, there has been a proposal to use an inductor L to tune point A and B at the frequency of the LO, to lower the effect of noise mixing down.
Although the Gilbert-type double balanced mixer circuit 100 of FIG. 1 is simple and used a lot in bipolar technology, it has some disadvantages in deep sub-micron CMOS technology. First, the low supply voltage in deep sub-micron CMOS technology limits the linearity of the mixer. It is a three-layer device and each layer of the device eats into the voltage headroom. The voltage swing on the resistor load should be smaller than the supply voltage minus the voltage headroom of the three layer transistors, otherwise the output is distorted and linearity becomes worse. Second, the flicker noise hurts the mixer noise performance when NMOS transistors and direct conversion receiver architecture are exploited, which is the most popular and simple architecture for a wireless receiver and results in a smaller RF receiver chip. Although a full PMOS transistor implementation serves as another candidate, the low threshold frequency fT of the PMOS transistor resists this substitution because it doesn't work well when used as an RF input amplifier pair inside the mixer. Third, this type of mixer suffers from the mismatch problem because of its feature size amplifier transistors, which have poor matching characteristics over the larger devices, and whereby the quadrature current sources are mismatched as well.
The matching requirement of the LO switching transistors are relaxed compared with the others because the input LO signal has a large swing and saturates the switching device quickly. Because of the offset introduced by mismatches, the even order inter-modulation cannot be cancelled completely through a differential circuit and the even order linearity becomes worse than what is typically assumed. Furthermore, the bias voltage of the LO signals should be a little bit higher than what it is needed in the general case to accommodate the process variation, which also eats into the voltage headroom.
To increase the linearity performance of the mixer, several modifications have been done to the primitive Gilbert-type double balanced mixer circuit 100 of FIG. 1. FIG. 2 shows a first revised Gilbert double balanced mixer circuit 200 as is known in the art, whereby the RF differential signal pair RFP, RFN are injected into the circuit through coupling capacitors C1, C2 and current-voltage (I-V) conversion, which down converts to a low frequency directly by the use of switching transistors. The whole circuit is biased by two separate DC current sources that are provided with a BIAS signal.
The first revised Gilbert double balanced mixer circuit 200 of FIG. 2 provides for more voltage headroom to the mixer circuit and has better linearity performance, as compared to the mixer circuit 100 of FIG. 1. However, it still has the shortcoming of high flicker noise being converted in-band when NMOS transistors and a direct conversion architecture are used. Also, the even order signal distortion introduced by the mismatch of current source is not improved and still poses a problem with respect to linearity of the mixer.
FIG. 3 shows a second revised Gilbert type double balanced mixer circuit 300, which improves on the mixer circuit 200 of FIG. 2. The input RF amplifier transistors T1, T2 are biased by an external mirror circuit (see resistors R1, R2, capacitors C1, C2, and bias signal BIAS) and have a certain gain at RF frequency. Since the voltage overhead of the amplifier transistors T1, T2 is lower than that of the DC current source, the voltage headroom of the second revised mixer circuit 300 of FIG. 3 is larger than that of FIG. 2. However, the RF input transistor pair contributes to the distortion, so one can only compare the linearity performance of the mixer circuit 200 as shown in FIG. 2 and the mixer circuit 300 as shown in FIG. 3 on a case by case basis. Also, it still has the same problem of flicker noise and even order non-linearity as the mixer circuits 100, 200 of FIG. 1 and FIG. 2.
To improve the noise performance of a down-conversion mixer in a direct conversion RF receiver, a folded PMOS double balanced mixer circuit 400 has been provided as shown in FIG. 4, whereby the mixer circuit 400 corresponds to an ‘active’ mixer. As shown in FIG. 4, PMOS transistors P1, P2, P3, P4 are used as the switching devices to perform the frequency conversion, and the RF input signal differential pair RFP, RFN are fed in through NMOS transistors N1, N2. In this way, the speed limit of the PMOS transistor in the RF range is avoided, whereby it is hard to get a reasonable gain because of low fT. However, there is no such tight limitation in the switching transistors because it is driven by arbitrary large LO signals LOP, LON and works nonlinearly. Since the flicker noise of PMOS devices is much smaller than that of NMOS devices, the in-band noise performance of the PMOS mixer is better than the NMOS mixer. Also, because of the folding architecture, the mixer circuit 400 of FIG. 4 has more voltage headroom as compared with the NMOS Gilbert type double balanced mixer circuit 100 shown in FIG. 1, and the linearity performance is better. However, the even order non-linearity of the mixer circuit 400 of FIG. 4 introduced by mismatch is not improved and the LO biasing is sensitive to process variations.
The conventional mixer circuits described above belong to the active mixer classification, whereby these mixer circuits switch the current to a resistor load under the control of LO signals and which does the signal frequency translation. There is another type of mixer circuit which uses a voltage sample-and-hold circuit to do the down-conversion of the RF signals, in which no DC current flows through the switching transistors, whereby such a mixer circuit is categorized as a ‘passive’ mixer.
FIG. 5 shows a conventional NMOS double balanced passive mixer circuit 500. The RF input differential pair RFP, RFN are fed into the mixer circuit 500 through two coupling capacitors C1, C2, which also serve as a DC isolator between the mixer circuit 500 and a previous stage (not shown) of a wireless circuit. The output OP and ON are biased at the desired voltage. During operation of the mixer circuit 500, the switching transistors T6, T7, T8, T9 are controlled to be open or close by the LO signals LOP and LON. When the switch is closed, it tracks the input voltage; when the switch is open, the tracked voltage is held. The frequency translation is done through this track-and-hold of the switch.
Since there is no DC current in a passive mixer, it has the potential for extremely low-power operation considering that CMOS technology offers excellent switches. However, the passive mixer circuit 500 of FIG. 5 has the following drawbacks: 1) Although the single balanced passive mixer with even order linearity problem may have positive gain, the double balanced one is generally with loss, whose noise performance is not good; 2) The transistor switches slowly compared with the one that has DC bias current, which is regarded as a voltage controlled resistor and degrades the linearity; 3) Although there is no DC current in the NMOS transistor, the flicker noise cannot be removed because there is still instantaneous charging and discharging current that includes the channel flicker noise; and 4) Since the passive mixer uses voltage track-and-hold, it is sensitive to device mismatch. All of these drawbacks results in the decreased popularity of the passive mixer in an RF receiver design.
An RF front-end with merged LNA and mixer has also been explored for use in an RF receiver design, as shown by the mixer/LNA circuit 600 in FIG. 6. The circuit 600 includes a differential LNA 610 and a double balanced mixer 620. The main purpose of this design is to reuse the DC current of the LNA and the mixer, which lowers the total power consumption of the RF front-end. Since it still uses a similar architecture as shown in FIGS. 1, 2 and 3, and the circuit voltage headroom is not increased, the performance is not improved very much if at all.